
NXP Semiconductors
PCA9685
16-channel, 12-bit PWM Fm+ I 2 C-bus LED controller
SDA
t BUF
t r
t f
t HD;STA
t SP
t LOW
SCL
t HD;STA
t SU;STA
t SU;STO
P
S
t HD;DAT
t HIGH
t SU;DAT
Sr
P
002aaa986
Fig 31. Definition of timing
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 1
(D1)
bit 0
(D0)
acknowledge
(A)
STOP
condition
(P)
t SU;STA
t LOW
t H IG H
1 / f SCL
SCL
SDA
t BUF
t r
t f
t HD;STA
t SU;DAT
t HD;DAT
t VD;DAT
t VD;ACK
t SU;STO
002aab285
Rise and fall times refer to V IL and V IH .
Fig 32. I 2 C-bus timing diagram
V I
OE input
V SS
V M
t PLZ
V M
t PZL
LEDn output
LOW-to-OFF
V DD
V M
OFF-to-LOW
LEDn output
V OL
V OH
t PHZ
V X
V Y
t PZH
HIGH-to-OFF
V M
OFF-to-HIGH
V SS
outputs
enabled
outputs
disabled
outputs
enabled
002aad810
Fig 33. t PLZ , t PZL and t PHZ , t PZH times
PCA9685
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 2 September 2010
? NXP B.V. 2010. All rights reserved.
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